In the semiconductor industry it is common to form a layer of crystalline silicon (generally referred to as an active layer) on an insulating layer to reduce any effects or interactions between the substrate (or handle wafer) on one side of the insulating layer and components formed on or in the crystalline layer on the other side of the insulating layer. At the present time the preferred insulating layer is formed of silicon dioxide (SiO2) because of the ease in forming the layer and because bonding between the silicon dioxide and the silicon of the handle wafer is easy to achieve. In this disclosure the term “crystalline silicon” is used to denote a layer of silicon that is substantially single crystal material, i.e. as much of a single crystal as can be formed using present day techniques.
One common method of forming a silicon dioxide insulating layer between a substrate and a crystalline silicon layer is to provide two silicon substrates and form a layer of silicon dioxide on the surface of one of the substrate. At present the film of silicon dioxide is almost always formed by thermal oxidation, i.e. heating the substrate in a high humidity (such as steam). The silicon dioxide surface is then brought into contact with the surface of the second silicon substrate and forms a molecular bond through a well known process, referred to in the industry as Van der Waal's bonding. One of the substrates is then partially removed by any of several different methods to leave a thin crystalline layer of silicon on the silicon dioxide layer. This in effect forms a buried oxide (BOX) insulator layer.
One method of removing a substantial portion of the substrate is to implant hydrogen, which is then annealed to form a weakened fracture plane. The substrate is then cleaved at the fracture plane and the surface is polished to a mirror surface using well known chemical mechanical polishing (CMP) techniques. Some methods have been introduced to improve the cleaving and polishing, see for example U.S. Pat. No. 6,372,609, entitled “Method of Fabricating SOI Wafer by Hydrogen ION Delamination Method and Wafer Fabricated by the Method”, issued Apr. 16, 2002.
One problem with the crystalline silicon on a silicon dioxide insulating layer is the strain produced by stress introduced at the junction by the lattice mismatch between the silicon and the thermally formed silicon dioxide. The lattice mismatch results in a relatively high compressive stress at the junction between the two materials. In many instances this high stress can result in dislocations, crystalline defects, and even fractures in the active layer. Some components can be formed in the crystalline layer that use this compressive stress to an advantage, however, since the compressive stress will be across the entire wafer it will affect all components formed in/on the crystalline layer, many to a highly undesirable degree. To provide an unstressed or unstrained active layer, the thickness of the silicon dioxide layer must be severely limited to a thickness at which the stress substantially disappears. That is, in each atomic layer of the silicon dioxide a small amount of the stress can be removed by lattice matching until, ultimately, all stress is removed (stress distribution). However, the result is a layer of silicon dioxide that is too thick to be of use in many applications, such as gate oxides in very small field effect transistors and the like.
Also, because the silicon dioxide layer allows some migration of impurities into the active layer from the substrate (handle wafer) both of the substrates must be high quality wafers, which adds substantial expense. Further, the silicon dioxide may contain impurities (e.g. hydrogen molecules introduced during the oxidation process) that can migrate into the active layer.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide new and improved semiconductor-on-insulator semiconductor wafers.
Another object of the invention is to provide a new and improved semiconductor-on-insulator semiconductor wafer with a stress engineered insulative/active layer to produce an active layer with a desired amount of compressive stress, a desired amount of tensile stress, or no stress.
Another object of the invention is to provide new and improved semiconductor-on-insulator semiconductor wafers that can be formed very thin.
And another object of the invention is to provide new and improved semiconductor-on-insulator semiconductor wafers with an insulating layer that prevents impurities from migrating into the active layer.
Still another object of the present invention is to provide new and improved semiconductor-on-insulator semiconductor wafers that can be formed with a less expensive handle wafer.